The present invention relates to the field of interconnects in semiconductor devices, and more particularly, to methods for forming single damascene and dual damascene structures in low dielectric constant materials.
Integrated circuit fabrication typically begins with a thin, polished slice of high-purity, single crystal semiconductor material, usually silicon. Junctions (which make up devices) are formed between field oxide portions of the semiconductor slice. Metal lines in conductor layers provide necessary electrical connections between the devices. Dielectric (i.e. insulating) layers are formed between the conductor layers to isolate the metal lines from each other. Vias provide conducting paths through the dielectric layers to connect the interconnects of different conductor layers.
In high performance integrated circuits in the sub-0.25 xcexcm regime, there is a need to fabricate interconnects using so-called damascene techniques. This is because conventional deposition and etching of aluminum-based metalization becomes increasingly difficult at these feature sizes. At the same time, performance considerations call for the use of lower resistivity metals such as copper, which has proven virtually impossible to pattern using conventional reactive ion etching. The desire to use copper for interconnects has increased the attractiveness of damascene techniques and spurred investigation into improving these techniques.
In addition to using low resistivity metals such as copper, circuit performance enhancement has been sought by combining the copper conductors with low dielectric constant insulators (k less than approximately 4). In many cases, these low k materials are spin coated polymers which are incompatible with conventional photoresist stripping using oxygen ashers or solvents. The patterning of the low k materials to form the trenches and vias of a damascene formation is a difficult task due to the incompatibility of the low k materials with conventional photoresist stripping.
An example of a single damascene process using a low k dielectric material is depicted in FIGS. 1A through 1D. A low k dielectric material 42 such as benzqcyclobutene (BCB), hydrogen silsesquioxane (HSQ) or the material known as FLARE (manufactured by Allied Signal) is spun on an interconnect layer 40. A cap layer 44 is then deposited on the low k dielectric layer 42. The cap layer 44 may be a 2000 xc3x85 thick layer of TEOS, or a multiple layer cap layer. For example, a multiple layer cap layer 44 may have a bottom 2000 xc3x85 thick TEOS layer, a 1000 xc3x85 thick nitride middle layer and a 800 xc3x85 thick top layer that is an organic bottom anti-reflective coating (BARC). A photoresist layer 46 is then deposited, leaving the structure of FIG. 1A.
The photoresist layer 46 is then patterned with the desired pattern and after developing, the cap layer 44 is etched, resulting in the structure of FIG. 1B. The etch recipe for the cap layer 44 is a different one than for the low k dielectric layer 42, which is an organic etch.
The photoresist layer 46 is then stripped off, using an appropriate oxygen ashing and/or solvent technique. This results in the structure of FIG. 1C. The cap layer 44 is used as a hard mask to pattern the low k dielectric layer 42 by an organic etch. This results in the structure of FIG. 1D. The cap layer 44 may be retained if it is TEOS only, although interconnect capacitance increases with TEOS thickness. The cap layer 44 is stripped if a multiple layer hard mask is employed.
An example of a dual damascene process sequence using a low k dielectric, having trenches with underlying via holes that are etched in the low k dielectric material before metal deposition and chemical-mechanical polishing (CMP), is depicted in FIGS. 2A-2D. This commonly used method of forming the trenches together with the via holes employs etch stop layers and photoresist masks. A bottom stop layer 14, such as silicon nitride, has been deposited over an existing interconnect pattern formed in an interconnect layer 10. The interconnect pattern may be formed from a conductor 12, such as copper. A layer of low k dielectric material 16 is then deposited on the bottom stop layer 14. The via will be formed within this low k dielectric layer 16.
A middle stop layer 18, such as silicon dioxide, is deposited over the low k dielectric layer 16. A via pattern 20 is etched into the middle stop layer 18 using conventional photolithography and appropriate anisotropic dry etching techniques. (These steps are not depicted in FIG. 2A. Only the resultant via pattern 20 is depicted in FIG. 2A.) The photoresist used in the via patterning is removed by an oxygen plasma, which consumes some of the exposed low k material, as indicated in FIG. 2A.
FIG. 2B depicts the structure of FIG. 2A after a second layer 22 of low k dielectric material has been spin coated on the middle stop layer 18 and through the via pattern opening 20. The structure is planarized at the same time. Following the spin coating and the planarization of the low k dielectric layer 22 in which the trench will be formed, a hard mask layer 24 is deposited. The hard mask layer 24 may be silicon dioxide, for example.
The trench pattern is then formed in a photoresist layer (not depicted) which is aligned over the via pattern, using conventional photolithography. The structure is then exposed to an anisotropic dry etch configured to etch through the hard mask layer 24. The etch chemistry is then changed to one which selectively etches the low k dielectric material in the low k dielectric layer 22, but not the hard mask layer 24 nor the middle and bottom stop layers, 18 and 14. In this way, a trench 26 and a via 28 are formed in the same etching operation.
In most cases, the low k etch chemistry etches the photoresist at approximately the same rate as the low k dielectric. The thickness of the trench photoresist is selected to be completely consumed by the end of the etch operation, to eliminate the need for photoresist stripping. This results in the structure depicted in FIG. 2C, in which all of the photoresist has been stripped and the trench 26 and via 28 have been formed. The bottom stop layer 14 is then removed by a different selective dry etch chemistry designed not to attack any other layers in order to expose conductor 12 to which the via is making a connection. The resulting structure is depicted in FIG. 2D. The bottom stop layer is normally used to protect the pre-existing interconnect layer from oxidation or corrosion during dry etching. If such concerns do not exist, bottom stop layer 14 and the corresponding bottom stop etching step are omitted.
In the known single and dual damascene processing techniques described above, the low k dielectric material is protected during removal of the photoresist by a mask (or cap) layer, formed of silicon dioxide or TEOS, for example. The patterning of the mask layer involves the separate steps of depositing and patterning a photoresist, and using the patterned photoresist in the etching of the mask layer. Hence, the need to protect the low k material during photoresist removal and pattern the protective mask adds a number of steps to the manufacturing process and therefore increases cost.
There is a need for a method of producing damascene structures in an interconnect arrangement incorporating low k dielectric materials with a reduced number of process steps while still protecting the low k dielectric layers from unintended etching and removal.
This and other needs are met by the present invention which provides a method of forming a damascene structure in a semiconductor device comprising the steps of forming a first low k dielectric layer and depositing an imageable layer on the first low k dielectric layer. The imageable layer is patterned to create a pattern with an opening in the first imageable layer. Silicon is then incorporated into the pattern of the first imageable layer. At least a portion of the first imageable layer with the incorporated silicon is converted into a hard mask and is positioned to protect the first low k dielectric layer from being etched except through the opening.
In certain embodiments, the imageable layer is an alicyclic polymer. A liquid silylation step is performed to incorporate silicon (approximately 10%-30% by weight, depending on the silylating agent used) is incorporated into the alicyclic polymer. When exposed to the etching step that etches the first low k dielectric layer, the silicon-rich regions in the imageable layer are at least partially converted to silicon dioxide, which acts as a hard mask to protect the unexposed portions of the first low k dielectric layer. Hence, a simple oxygen plasma etch simultaneously is used in a single step to etch low k dielectric material and convert the silicon-rich regions of the imageable layer to a hard mask. Since the hard mask has a very high etch resistance, only a thin layer (e.g. about 250 nm) may be employed as the imageable layer. The imageable layer does not need to be stripped and can remain in place since it is a dielectric material itself. Also, since only a thin layer of the imageable layer is originally deposited, the interconnect capacitance will not be greatly increased by the retention of this layer within the interconnect structure. This compares favorably with prior art structures which employ silicon dioxide layers (such as TEOS) of 2,000 xc3x85 thickness that remain in place in the final arrangement.
The earlier stated needs are met by another embodiment of the present invention in which a dual damascene structure is created by forming a second low k dielectric layer on the first imageable layer. A second imageable layer is then deposited on the second low k dielectric layer. The second imageable layer is patterned to create a trench opening in the second imageable layer. At least a portion of the trench opening overlays the via opening. Silicon is then incorporated into the second imageable layer. The first and second low k dielectric layers are etched through the trench opening and the via opening. This etching process transforms the second imageable layer and portions of the first imageable layer exposed by the trench opening into hard mask regions.
The present invention has the advantage of reducing the number of process steps required to create a dual damascene structure while protecting the low k dielectric material in the arrangement. This is due to avoiding the use of conventional photoresist material and the stripping steps required to remove this material. Instead, a single imageable layer is used on the low k dielectric material that can be imaged into a pattern, and after a liquid silylation to incorporate silicon, the transformed the hard mask layer in the simultaneous step that the etching of the low k dielectric material through the opening in the imageable layer.
In addition to the methods for creating damascene structures provided by the present invention, the earlier stated needs are also met by an interconnect arrangement in a semiconductor device comprising a first low k dielectric layer and a first alicyclic polymer layer on the first low k dielectric layer. The first alicyclic polymer layer has a hard mask region. A via is formed in the first low k dielectric layer and a hard mask region in the first alicyclic polymer layer. A second low k dielectric layer is provided on the first alicyclic polymer layer. A second alicyclic polymer layer is on the second low k dielectric layer. The second alicyclic polymer layer has a hard mask region. A trench is formed in the second low k dielectric layer and the hard mask region in the second alicyclic polymer layer.
The interconnect arrangement of the present invention has a very thin layer separating the first and second low k dielectric layers, much thinner than prior arrangements which employ a silicon dioxide layer of approximately 2,000 xc3x85. By reducing the thickness of the mask layer between the dielectric layers, the total capacitance of the interconnect arrangement is reduced according to the present invention. In certain preferred embodiments, the thickness of the imageable layer is about 250 nm.
Furthermore, the use of an imageable layer having regions that are convertible to a hard mask provides dual functionality in a single layer, (i.e. imaging and masking) to allow reduction in the number of processing steps and simplification of the procedure by which organic low k dielectric material is protected from consumption by exposure to oxygen. If conventional photoresist stripping is employed as in the prior art, for example, the organic low k dielectric material would be consumed without appropriate masking. This is avoided by the present invention in which the imageable layer protects the low k dielectric material and has portions that are actually converted into a hard mask during the process in which the low k dielectric material is etched.
The foregoing and other features, aspects and advantages of the present invention will become apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.